In one known method for testing large digital systems such as digital integrated circuits, the elements of the system are partitioned into combinational networks and scannable memory elements. The scannable memory elements have a parallel or normal operation mode in which they are connected to the combinational networks of the system to provide memory functions required to perform the intended functions of the system. The scannable memory elements also have a serial or scan mode in which they are decoupled from the combinational logic and connected in series to form a shift register. Such partitioning and provision of scannable memory elements is known as Level Sensitive Scan Design (LSSD).
Digital systems employing LSSD are tested by configuring the scannable memory elements in serial mode, shifting a known test stimulus pattern into the shift register, reconfiguring the scannable memory elements into parallel mode, running the system clock through a single clock cycle, reconfiguring the scannable memory elements into serial mode, and shifting a test result pattern out of the shift register. The test result pattern is compared with a calculated test result pattern or with a test result pattern obtained from combinational logic known to be functioning properly to determine whether the combinational logic under test is functioning properly.
Typical LSSD techniques are described in U.S. Pat. No. 3,761,695 issued Sept. 25, 1973 and U.S. Pat. No. 3,783,254 issued Jan. 1, 1974, both in the name of E. B. Eichelberger, and in U.S. Pat. No. 4,293,919 issued Oct. 6, 1981 in the names of Dasgupta et al.
The LSSD technique has a number of disadvantages. Appropriate test stimulus patterns must be generated and corresponding test result patterns must be calculated or measured. This requires appropriate algorithms, computational facilities and skilled personnel. Memory must be provided for storage of test stimulus patterns and corresponding test result patterns until they are required for test application. Most importantly, the scannable memory elements and the combinational logic to be tested must be reconfigured after each test stimulus pattern in order to apply test stimulus patterns and to read out test result patterns, and the test stimulus patterns and test result patterns must be transmitted between external test equipment and the system under test via interconnecting cables which limit test clock operation to rates lower than the normal operating clock rate. Consequently, test conditions do not correspond exactly to normal operating conditions and faults unique to the normal operating conditions may go undetected. Moreover, the use of reconfigurable memory elements embedded throughout the digital system increases design complexity and cost, and compromises the performance of the resulting system.
In another technique, known as the boundary or peripheral scan technique, a digital system is partitioned according to its physical partitioning onto a number of integrated circuits. A scannable memory element is provided at each input and output pin of each integrated circuit. These memory elements have a parallel or normal operation mode in which they connect internal circuitry of the integrated circuits to the input and output pins to permit normal operation of the integrated circuit. The memory elements may or may not provide memory functions required in normal operation of the integrated circuits. The memory elements also have a serial or scan mode in which they are decoupled from the internal circuitry of the integrated circuits and connected in series to form shift registers.
The internal circuitry of integrated circuits having boundary scan architectures is tested by configuring the scannable memory elements in serial mode, shifting a known test stimulus pattern into memory elements which correspond to circuit inputs, reconfiguring the scannable memory elements into parallel mode, running the system clock through a single clock cycle, reconfiguring the scannable memory elements into serial mode, and shifting a test result pattern out of memory elements of the boundary register corresponding to circuit outputs. The test result pattern is compared with a calculated test result pattern or with a test result pattern obtained from an integrated circuit known to be functioning properly to determine whether the integrated circuit under test is functioning properly.
External circuitry interconnecting integrated circuits having boundary scan architectures is tested by configuring the scannable memory elements of the integrated circuits into serial mode, shifting a known test stimulus pattern into the scannable memory elements, reconfiguring the scannable memory elements into parallel mode to interconnect the outputs of the integrated circuits to the inputs of other integrated circuits via the external circuitry, clocking the memory elements to transfer bits of the test stimulus pattern over the external circuitry to the inputs of the other integrated circuit, reconfiguring the scannable memory elements into serial mode, and shifting a test result pattern out of the scannable memory elements. The test result patterns are compared with calculated test result patterns or test result patterns from integrated circuits having interconnections known to be good to determine whether the external circuitry is functioning properly.
Boundary scan architectures and techniques may be combined with LSSD architectures and techniques by providing scannable memory elements at inputs and outputs to the integrated circuit while also making scannable at least some of the memory elements which are internal to the integrated circuit.
Typical boundary scan architectures and techniques are described in "A Standard Boundary Scan Architecture", Version 1.0, Technical Subcommittee of the Joint Test Action Group (JTAG), June 1987.
The boundary scan technique overcomes some of the problems of the LSSD technique. In particular, the scannable memory elements are restricted to the periphery of the functional logic system to be tested, thereby reducing design complexity and cost. Moreover, the scannable memory elements are not generally needed for normal operation of the functional logic system and can be bypassed in the normal operation mode of the systems to avoid compromising performance of the system in its normal operation mode. The boundary scan technique also permits relatively straightforward testing of interconnections between digital systems.
However, the boundary scan technique does not overcome the need for generation of appropriate test stimulus patterns and calculation or measurement of corresponding test result patterns. Appropriate algorithms, computational facilities, skilled personnel, and memory for storage of test stimulus patterns and corresponding test result patterns are therefore required as in LSSD techniques. More importantly, the scannable memory elements must be reconfigured after each test stimulus pattern in order to apply test stimulus patterns and to read out test result patterns, and the test stimulus patterns and test result patterns must be transmitted between external test equipment and the system under test via interconnecting cables which limit test clock operation to rates lower than the normal operating clock rate as in LSSD techniques. Consequently, the test configuration does not correspond exactly to the normal operation configuration and certain subtle faults unique to the normal operation configuration may go undetected.
Built In Self Test (BIST) techniques overcome the need for external test stimulus pattern generation and storage by providing test stimulus pattern generators and test result pattern evaluators within the digital system to be tested. Because the test stimulus patterns and test result patterns need not be transmitted between external test equipment and the system under test via cables, the system can be tested at the normal operating clock rate. Consequently, faults which appear only at high clock rates will be detected.
For example, Konemann et al, IEEE Journal of Solid State Circuits, Vol. SC-15, No. 3, pp.315-319, June 1980 describes the use of linear feedback shift registers for generation of pseudo-random test stimulus patterns and for compression of test result patterns into test result signatures. The pseudo-random test patterns are applied to the circuitry under test, and test result patterns are extracted and accumulated into test result signatures. The test result signatures are compared to calculated signatures corresponding to circuitry known to function properly.
Combinations of BIST techniques with LSSD techniques are described in Krasniewski et al, 24th ACM/IEEE Design Automation Conference, Paper 24.4, pp.407-415, June 1987 and Stroud, 25th ACM/IEEE Design Automation Conference, Paper 3.1, pp.3-8, June 1988. Scannable memory elements of the circuit to be tested are connected to form a ring register, and each memory element includes an EXCLUSIVE OR gate which combines serial and parallel inputs to that memory element when the memory elements are configured in test mode. This arrangement provides test stimulus pattern generation and test result pattern compression within the shift register, thereby avoiding the need for test stimulus pattern generation and test result pattern compression external to the shift register as in more typical BIST architectures. Unfortunately, the scannable memory elements and the combinational logic to be tested must be reconfigured in order to apply test stimulus patterns and to read out test result patterns as in other LSSD techniques. As a result, test conditions do not correspond exactly to normal operating conditions and certain faults unique to the normal operating conditions may go undetected. Moreover, the use of reconfigurable memory elements embedded throughout the digital system increases design complexity and cost, and compromises the performance of the resulting system.
Another example of BIST techniques is described in U.S. Pat. No. 4,357,703 issued Nov. 2, 1982 in the name of Nicholas P. Van Brunt. An input shift register and an associated generator/accumulator provide a test stimulus pattern to the circuitry under test, and an output shift register and an associated generator/accumulator compresses the corresponding test result pattern into a test result signature. Interconnections between integrated circuits are tested by generating test patterns at the output generator/accumulator of one circuit and compressing corresponding test result patterns at the input generator/accumulator of downstream integrated circuits. However, the requirement for separate input and output shift registers and generator/accumulators complicates interconnection of the shift registers to the circuitry under test since the circuit inputs and outputs may typically be arranged in any order on the periphery of the integrated circuit.